MicroZed Chronicles: Working with the Kria SOM in Vivado
The Kria KV260 Vision AI Starter Kit is great for embedded vision applications and AI acceleration. Several of my clients, however, have...
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adam14204
- Aug 25, 2021
- 2 min
MicroZed Chronicles: Example Designs in Vivado and Vitis
Over the years, several blogs and projects have leveraged the Vivado and Vitis ability to generate example projects. One of the most...
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adam14204
- Aug 25, 2021
- 4 min
MicroZed Chronicles: A Blast from the Past!
Modern FPGA devices really spoil us. They include PLLs, DCM, DSP etc. and a range of interfaces that significantly ease our developments....
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: Designing in DDR to your FPGA
Over the last two months, I have had several clients approach me for help regarding DDR3 / DDR3L interfaces that they have connected to...
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adam14204
- Aug 25, 2021
- 5 min
MicroZed Chronicles: Multi-Gigabit Transceivers
One aspect of FPGA design that we haven’t really examined is multi-gigabit transceivers (MGT). These transceivers are available in many...
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adam14204
- Aug 25, 2021
- 4 min
MicroZed Chronicles: Implementing Safe State Machines with Vivado
I thought I would examine how we can implement safe state machines when using Vivado 2020.2 and Xilinx synthesis
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: Using Analysis View in Vitis and Vivado
One of the most useful views available in both Vivado HLS and Vitis HLS is the analysis view.
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: Free Virtual Workshops On-Demand
This past summer, I was lucky to present several detailed virtual workshops on Vivado, PYNQ, Vitis, and more. They are available on-demand.
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: AXI Stream Verification IP
The AXI Stream VIP is extremely useful when we want to generate signal and image processing IP that use AXI Stream for interfacing.
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adam14204
- Aug 25, 2021
- 4 min
MicroZed Chronicles: Verifying AXI Peripherals
The designs we implement in Vivado often use AXI interfaces. These might be AXI Lite for configuration and control, AXI Memory Mapped
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adam14204
- Aug 25, 2021
- 4 min
Using SLX FPGA in Vitis bottom up flow
Last year, I examined SLX FPGA and used it to optimize IP Cores for implementation in Vivado looking at security and industrial algorithms.
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adam14204
- Aug 25, 2021
- 4 min
MicroZed Chronicles: Vivado Simulator Interface – Using C Test Benches on HDL
For complex algorithms, it is often a good idea to first create a model which defines the algorithm’s behavior.
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adam14204
- Aug 25, 2021
- 4 min
MicroZed Chronicles: Introduction to RTL Simulation and XSIM
No matter how captured (RTL, HLS, Model Driven), all programmable logic designs should start with agreed requirements that define the...
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: RTL Design Verification Techniques
So, before we look in more detail at Vivado XSIM, let’s first understand the entire verification landscape and what we are trying to achieve
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: UltraFast Design Methodologies
Using Xilinx UltraFast design methodologies can offer significant benefits when implementing designs.
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adam14204
- Aug 25, 2021
- 3 min
MicroZed Chronicles: Quality of Result
In this blog we explore the Quality of Result Assessment (QoRA) and Quality of Result Suggestions (QoRS).
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